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宏碁將即將過期專利價值最大化，轉手購自NEC專利再轉讓給NPE
標準必要專利(SEP)即將專利到期，怎麼辦？何不學學宏碁，將它轉手給NPE來協助將價值最大化。
宏碁於2020年11月將原本於2009年自NEC取得的專利USP# 6671750，轉讓給Rock Creek Networks, LLC後，該 '750專利已陸續在美國德州西區聯邦法院提起七起專利侵權訴訟，有關網路介面技術。
截至目前為止，相關訴訟案的被告，包含：華為、富士通、CASwell與四家網通相關台商瑞昱（Realtek Semiconductor Corp.）；合勤科技（Zyxel Communications Corp.）；威盛電子（VIA Technologies, Inc.）；友訊科技（D-Link Corp.）。....
【Talk】A New SAR ADC Architecture
Invite you all interested people to join it !!!
Time : Sep. 23(Wed. 5:00~6:00 pm), 2015
Venue : Conference Hall (合勤講堂), Basement 1st, Engineering Building 4, National Chiao Tung University
交通大學(光復校區)工程四館地下一樓 合勤講堂
Speaker : Prof. Behzad Razavi
University of California, Los Angeles
Sponsored by : Realtek Semiconductor Corp.
Organized by : Department of Electronics Engineering, NCTU
Abstracts :
SAR ADCs have shown great promise for low-power design. The speed of SAR architectures can be improved through the use of interleaving or multi-bit conversion, each posing its own trade-offs. Specifically, multi-bit schemes employ several DACs, incurring a large area penalty and a high input capacitance.
This presentation proposes the use of VCOs as multi-bit quantizers in a SAR environment. Resolving 3 bits per cycle, this approach also allows shorter LSB conversion times by adjusting the VCO gain on the fly. A 40-nm CMOS prototype incorporates two VCOs and a TDC along with background calibration. The 12-Bit 200-Ms/s ADC consumes 3.4 mW with a 0.85-V supply. At the Nyquist rate, the SNDR is 68 dB and the FOM 8 fJ/conv. step.
Bio :
Behzad Razavi is Professor of Electrical Engineeirng at UCLA, where he conducts research on analog and RF integrated circuits. An IEEE Fellow and Distinguished Lecturer, Prof. Razavi has published more than 180 papers and seven books. He has received seven IEEE best paper awards and four teaching awards, and his books have been published in seven languages. He received the 2012 IEEE Pederson Award in Solid-State Circuits.
Contact：NCTUEE / Patty Chen 03-5712121#54107 patty@mail.nctu.edu.tw
【Talk】A New SAR ADC Architecture
Invite you all interested people to join it !!!
Time : Sep. 23(Wed. 5:00~6:00 pm), 2015
Venue : Conference Hall (合勤講堂), Basement 1st, Engineering Building 4, National Chiao Tung University
交通大學(光復校區)工程四館地下一樓 合勤講堂
Speaker : Prof. Behzad Razavi
University of California, Los Angeles
Sponsored by : Realtek Semiconductor Corp.
Organized by : Department of Electronics Engineering, NCTU
Abstracts :
SAR ADCs have shown great promise for low-power design. The speed of SAR architectures can be improved through the use of interleaving or multi-bit conversion, each posing its own trade-offs. Specifically, multi-bit schemes employ several DACs, incurring a large area penalty and a high input capacitance.
This presentation proposes the use of VCOs as multi-bit quantizers in a SAR environment. Resolving 3 bits per cycle, this approach also allows shorter LSB conversion times by adjusting the VCO gain on the fly. A 40-nm CMOS prototype incorporates two VCOs and a TDC along with background calibration. The 12-Bit 200-Ms/s ADC consumes 3.4 mW with a 0.85-V supply. At the Nyquist rate, the SNDR is 68 dB and the FOM 8 fJ/conv. step.
Bio :
Behzad Razavi is Professor of Electrical Engineeirng at UCLA, where he conducts research on analog and RF integrated circuits. An IEEE Fellow and Distinguished Lecturer, Prof. Razavi has published more than 180 papers and seven books. He has received seven IEEE best paper awards and four teaching awards, and his books have been published in seven languages. He received the 2012 IEEE Pederson Award in Solid-State Circuits.
Contact：NCTUEE / Patty Chen 03-5712121#54107 patty@mail.nctu.edu.tw
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