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關於verilog casez 在 Re: [sv-bc] Enhancement Request: 2-state wildcard ... 的評價
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verilog casez 在 Re: [問題] verilog中if else和case合成後的差別- 看板Electronics 的推薦與評價

作者zangtingzhen (渟沂)

看板Electronics

標題Re: [問題] verilog中if else和case合成後的差別

時間Sat Sep 8 19:16:47 2012

※ 引述《hadbeen (你在哪)》之銘言：
假設可能的a只有0~10000之間

case(a)
0:---------------\
. \
. 執行ins1
. /
. /
10:---------------/
11:----------------\
. \
. 執行ins2
. /
. /
100:----------------/
101:--------------\
. \
. \
. 執行ins3
. /
1000:--------------/
1001:------------\
. \
. \
. 執行ins4 假設是個nmos
. / 這個gate電壓為:
10000:------------/ 1:如果a=0
0:elsewhere
↓
以上我可以想像每個case合成後變以a=0的來說 ins1 ----|￣￣|----->執行的內容

共有一萬個像這樣的transmitting gate組成一個超大多工器

各各平行即同一時間只有一個transister會通

那寫成
if(a>1000) 執行ins4

else if(a>100) 執行ins3

else if(a>10) 執行ins2

else 執行ins1

應該也是合出上面同義(function上同義)case敘述所合成出的電路吧?

那這樣的話兩種寫法差在哪?寫code的方便性嗎?(如果要寫case就要寫一大堆)

--

※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 114.32.239.249

我印象中在Advanced ASIC Chip Synthesis這本書講的coding style有提到過。

用if....else....的話會合出有"優先順序"的結構，就是會有串接的mux

a>1000
|
a>100 -----
| ---| |
----- |mux|----output
---| |-----| |
|mux| -----
---| |
-----

用case的話，每個輸入訊號是平行的，就是沒有優先順序

---------------
a --|combinational|----
--------------- |
|
------
-----| |
-----| |
-----|mux |----output
-----| |
-----| |
------

這本書是講design compiler的，聽說其它合成工具不一定會這樣~

有欠缺的話麻煩其他大大補充~

--

※ 發信站: 批踢踢實業坊(ptt.cc)
◆ From: 140.113.150.149

推 forever5566:推 09/08 23:29

推 mmonkeyboyy:正解不過現在的compiler有的會幫忙這件事了 09/09 02:00

→ mmonkeyboyy:但ISX這個東西一直到200X年都還沒有這個功能 09/09 02:00

... <看更多>

verilog casez 在 Verilog Case Statement: Understanding the Structure and ... 的推薦與評價

In this informative episode, the host explored a range of topics related to the Verilog case structure. The episode began with an ... ... <看更多>

verilog casez 在 Re: [sv-bc] Enhancement Request: 2-state wildcard ... 的推薦與評價

... casex/casez wildcards also match incoming X's > (which > can be dangerous). > I've attached a paper I've written on X-issues in Verilog - which won an ... <看更多>

verilog casez 在 Verilog (4) – 算術邏輯單元ALU 的設計(作者：陳鍾誠) 的推薦與評價

採用CASE 語法設計ALU. 其實、在Verilog 當中，我們並不需要自行設計加法器，因為Verilog 提供了高階的「+, -, *, ... ... <看更多>

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Casex synthesizable

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